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Task #3154

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TJ VS

Task #3046: Detailed Design

Design and Development of Controller+4G(N58) PCB

Task #3154: Design and Development of Controller+4G(N58) PCB

Added by Thomas Joseph about 2 months ago. Updated 22 days ago.

Status:
In Progress
Priority:
High
Assignee:
Target version:
-
Start date:
19/01/2026
Due date:
11/02/2026 (28 days late)
% Done:

93%

Estimated time:
(Total: 0:00 h)
Spent time:
2:00 h (Total: 49:00 h)

Description

Modify connector PCB considering the mech and electrical connection with IO PCB


Subtasks 3 (3 open0 closed)

Task #3126: Controller PCB BoMResolvedResmi K.V09/02/202611/02/2026

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Task #3163: Schematic DesignIn ProgressBhavani M19/01/202619/01/2026

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Task #3164: PCB DesignIn ProgressVenuMadhav S20/01/202611/02/2026

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TJ Updated by Thomas Joseph about 2 months ago Actions #1

  • Status changed from Resolved to New
  • Parent task set to #3046

TJ Updated by Thomas Joseph about 2 months ago Actions #2

  • Subject changed from Design and Development of Connector PCB(Modification) to Design and Development of Controller+4G(N58) PCB(Modification)

TJ Updated by Thomas Joseph about 2 months ago Actions #3

  • Subtask #3163 added

TJ Updated by Thomas Joseph about 2 months ago Actions #4

  • Subtask #3164 added

TJ Updated by Thomas Joseph 29 days ago Actions #5

  • Subject changed from Design and Development of Controller+4G(N58) PCB(Modification) to Design and Development of Controller+4G(N58) PCB
  • Status changed from New to In Progress

This is a new PCB design merging the schematics of GW2.0 PCBs (w/o Wifi)

TJ Updated by Thomas Joseph 29 days ago Actions #6

  • Subtask #3126 added

TJ Updated by Thomas Joseph 29 days ago Actions #7

  • Subtask #3246 added

TJ Updated by Thomas Joseph 29 days ago Actions #8

  • Subtask deleted (#3246)

TJ Updated by Thomas Joseph 27 days ago Actions #9

PCB design Guidelines

Schematic Review
-component clearances (>2mm for bigger components and ICs, >0.5mm upto 0805 components. Use 0.25mm placement grids or appropriately
-Place all the connectors as per mechanical, stacking requirement (SMA, SIM, uSD, reset, USB, LAN, headers for LED, PLCIO, Connector PCB, unused signals)
-Place major components considering SI of high speed/RF signals
-Place storage/decoupling capacitors at power entry points of all major components (Load)
-Place PDN components and passives
Review
-Optimise the placements
Review
-Course route of following signals
--RF Signals and Grounding
--USB (90 Ohm)
--MDI of LAN
--RMII of PHY
--uSD
Review
-Decoupling cap placing adj and routing
-Routing of power entry to decap
Review
-Adjust the placements if required
-Complete the planes/wide traces wherever required
-Thermal consideration for heat dissipating comp like LDO, DC-DC (put max. possible copper area)
Review
-Fine routing (adjust placements if required)
-Finish routing
Review
Gerber
Review

Note :
a. The stacking connectors at the opposite end of the edge where SMA USB LAN placed.
b. Provide max. space at the stacking connector to place serial interface components in future

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