Core4 » mDAQ4-1(Mid Range mDAQ)-Pilot

Planned to start porting on 22/01/2026

Code integrated for DI module.

For DI SPI clock and Chip set were generating but MOSI and MISO were not coming. It is observed that only one clock cycle is generating(8 pulses) but we need to write 16 bit data.

DI is tested with Different inputs AAAA, 5555,00FF,FF00,F0F0. In these 00FF,FF00,F0F0 these inputs were reflecting on the terminal and the respective waveforms were generated. And for toggling inputs like AAAA, 5555 we were not getting the output in the terminal.

https://elpisit-my.sharepoint.com/:x:/g/personal/satish_sl_elpisitsolutions_com/IQCLSJ5-TJFpQrp3hDAHWTrvAU3Fl2PXWkHaS3Tx6P4ysZM?e=fmKWuU-- this the test result link

Thomas sir suggested to test by changing the SPI CLK frequency to 100kHz or less to correct this issue